1. Technical Field of the Invention
The present invention relates to the field of testing of electronic circuits, and in particular to the testing of digital electronic integrated circuits.
2. Description of Related Art
A digital electronic circuit is customarily fabricated on the basis of what is called an RTL description (standing for “Register Transfer Level”) which describes the operations of the circuit in an appropriate programming language, for example, one of the C, Verilog or VHDL language (standing for “Very High Speed Integrated Circuit Hardware Description Language”). An RTL description can customarily be validated with the aid of simulation software tools.
A description at the logic level (called a “netlist”), describing a set of logic gates (corresponding to assemblies of transistors) and of connections, can be synthesized on the basis of the RTL description. The operation of a netlist can be validated by virtue of functional tests.
Steps of placement and routing lead to a drawing of the masks (called a “layout”) on the basis of the description at the logic level. Thereafter, what is called an LVS test (standing for “Layout versus Schematic”) can be executed so as to verify that the layout does indeed correspond to the logic description.
Then the circuit is fabricated on the basis of the layout.
The fabricated circuit must finally be tested so as to verify that no logic gate is “stuck” at a fixed value (“stuck at 0 or stuck at 1”), because of, for example, a short-circuit. To thus test the fabricated circuit, it is known to carry out what is called a scan test. Scan tests use the principle according to which any digital circuit consists of a relatively easy to test combinatorial part and of a sequential part limited to D-type flip-flops. The D-type flip-flops can be connected together by virtue of multiplexers to make it possible readily to control the signals dispatched or received from the combinatorial part.
FIG. 1 shows an exemplary digital part of a relatively simple electronic circuit able to be tested by a scan test. The digital part 1 comprises a sequential part 2 and a combinatorial part 3. The sequential part 2 comprises flip-flops 6A, 6B, 6C, . . . , of type D each associated with a multiplexer 80A, 80B, 80C, . . . , and grouped into a chain 2. Each of the flip-flops 6A, 6B, 6C, . . . , comprises a data input respectively 7A, 7B, 7C, . . . , a scan input respectively 8A, 8B, 8C, . . . , an output respectively 8B, 8C, 8D, . . . , a clock input, not represented, and an enabling input controlled by an enabling signal scan_en. When the enabling signal is at a logic “1” level, the logic state of the scan inputs 8A, 8B, 8C, . . . , is copied over to the corresponding outputs 8B, 8C, 8D, . . . , at each rising clock edge. On the other hand, when the enabling signal is in a logic “0” state, the logic state of the data inputs 7A, 7B, 7C, . . . , is copied over to the corresponding outputs 8B, 8C, 8D, . . . , at each rising clock edge.
The enabling signal scan_en also commands a switch 9. When the signal scan_en is in a logic “0” state, the signal scan_out at the output 5 of the electronic circuit takes the value of the signal Scomb at the output of the combinatorial part 3, termed the functional output. When the signal scan_en is in a logic “1” state, the signal scan_out at the output 5 takes the value of the signal Sseq at the output of the sequential part 2, termed the scan output.
FIG. 2 shows timecharts illustrating the manner of operation of a scan test of the digital part represented in FIG. 1.
Initially, the signal scan_en takes a nonzero value lasting, for example, five clock cycles, thus allowing shifts within the chain 2. The chain 2 comprising five flip-flops, five clock cycles are therefore necessary for loading the chain with new input values.
After these five cycles, the signal scan_en goes to zero. The outputs of the flip-flops then take values prescribed by outputs termed secondary 7B, 7C, 7D, 7E of the combinatorial part 3. The value of the signal Scomb is read at the output termed primary of the combinatorial part 3, that is to say the functional output.
This is subsequently followed by five new shift cycles within the chain, the signal scan_en having resumed a nonzero value. At each clock cycle, a value of the signal Sseq is read at the output of the chain 2. Stated otherwise, the secondary outputs are read one by one during these five cycles termed purge cycles. These five purge cycles make it possible furthermore to reload the chain with new input values.
Each sequence of five values of the input signal is called a test vector. Methods of automatic test program management or ATPG (standing for “Automatic Test Pattern Generator”) make it possible to generate test vectors intended to be placed at the input scan_in of the chain. The values of the signals of the test vectors are such that, if the fabricated circuit is operationally correct, all the connections must change value at least once during the conduct of the scan test.
In practice, for more complex digital circuits, the chain can comprise a relatively high number of flip-flops, for example, of the order of a thousand or some ten thousand. Such a chain length renders the duration of reading of the values of the secondary outputs relatively lengthy. The scan test is therefore also relatively lengthy.
It is known to arrange several relatively short chains rather than a single relatively long chain, so as to avoid excessive test durations. A single enabling input signal scan_en and a single clock signal clk can control all the chains. On the other hand, with each scan chain are associated an input scan_in and an output scan_out respectively. The number of pins required for performing the scan test therefore increases with the number of chains. This is a drawback.
Specifically, the complexity of the routing of the tracks of the card comprising the electronic circuit increases with the number of pins, as well as the risk of congestion. It may also be possible to reuse already hard-wired pins, in which case a multiplexer will have to be envisaged for each reusable pin, thereby running the risk of decreasing the speed of operation of the circuit. Furthermore, it may possibly be necessary to adapt the I/O cells of the pins to be reused so that the command cells support other types of signals. The consumption also increases with the number of pins.
An optimization between the number of pins and the duration of the test must therefore be performed.
In practice, the vectors generated by ATPG methods contain relatively little effective information. This is related to the very structure of combinatorial logic. It is known to profit from this ineffectiveness by using, as shown in FIG. 3, relatively short scan chains 21, 22, . . . ,2N. The scan chains 21, 22, . . . , 2N are loaded via a logic combination of a reduced number of inputs called pseudo scan_in at the pins 141, . . . , 14n. These logic combinations are carried out by a decompressor 10. The outputs of these short chains are connected to compression logic 13 whose outputs called pseudo scan_out are dispatched to the pins 151, . . . , 15n.
ATPG methods are capable of generating vectors termed compressed applicable directly to the pins 141, . . . , 14n. These vectors have a smaller length than the ATPG vectors, so that the duration of the test is then lower overall.
In FIG. 3, the digital part 12 comprises a tested part 11, decompression means 10 and compression means 13. The tested part 11 comprises a relatively high number N of chains 21, 22, . . . , 2N and combinatorial parts not represented in FIG. 3.
The tested part 11 is linked to an enabling pin 16, to a clock pin 17 and to a pin 18 for resetting to zero of the scan test.
Moreover, a command register 20 or TMC (standing for “Test Mode Control”) makes it possible to store certain command parameters of certain analog parts not represented, such as, for example, a phase-locked loop or PLL, or else yet another multiplexer. These parameters, for example, control the wiring of a PLL, or else also the programming of a multiplexer. The TMC 20 thus makes it possible to place the fabricated circuit in a desired mode, and in particular in a desired test mode. The TMC 20 can, for example, be programmed via a standard interface, for example, 12C (standing for “Inter Integrated Circuit”). This programming generally requires at least one digital pin 19.
The decompression means 10 make it possible to transform a relatively low number n of compressed input vectors into N chain input vectors. The compression means 13 make it possible to transform N chain output vectors into n compressed output vectors. N can, for example, be of the order of a hundred, while n can be of the order of about ten. It is thus possible to obtain relatively short test durations, on account of the number N of chains 21, 22, . . . , 2N, with a relatively low number 2*n of pins 141, 14n, 151, . . . , 15n.
However, a compression is effective only onwards of a certain number of vectors, typically 7 or 8. Thus, for n=8, the compression rate is about 50, so that N is about 400. For n=5, the compression rate is about 10 only. But, for a number n of 8, eight input pins 141, 14n and eight output pins 151, . . . , 15n dedicated to the scan test are required, i.e. sixteen pins to be added to the enabling pin 16, to the clock pin 17, to the pin for resetting to zero of the scan test 18 and to the digital pin 19.
Thus, in the case of circuits comprising a relatively reduced number of pins, this compression might not be performed in an effective manner, so that the duration of the test may still be relatively high.
The IEEE 1149.1 specification, the disclosure of which is hereby incorporated by reference, proposes the use of a state machine to decrease the number of pins dedicated to (that is to say reserved for) the scan test. The state machine is controlled by a certain number of pins dedicated to the state machine: a command pin TMS, a data pin TDI, a clock pin TCK, a resetting to zero pin TRSTN and an output pin TDO. The state machine makes it possible to transmit the data received at the data pin TDI to the input of the desired chain by using a predefined protocol. However, having regard to the complexity of the scan test, this management can turn out to be inoperative, in particular in the case of a compression.
Generally, the known scan tests require a certain number of pins reserved for the scan test. There is a need to limit the number of pins thus dedicated to the scan test, so as to reduce the associated proportions.